Effect of Shifting Gate Pulse on Output Voltage Ripple in Coupled SIDO Boost Converter

DC-DC converters that generate multiple DC outputs from single DC input are called single input multiple-output (SIMO) converters. The SIMO with two outputs is called a single input dual output (SIDO) converters. The SIDO converters are better than two separate single input single output (SISO) converters because of the reduced component count and increased efficiency. The coupled inductor SIDO (CI-SIDO) boost converter is analyzed in this paper. The CI-SIDO boost has two MOSFETs with two gate pulses. The methods of shifting gate pulse are introduced in CI-SIDO boost converters for reducing inductor current ripples. The shift in gate pulse changes the inductor current patterns and the capacitor current patterns. This may change the output voltage ripples; however, this is not investigated in the literature. The value of output voltage ripples decides the output capacitor value. If the shifting of gate pulses reduces the output voltage ripples, the value of the capacitor reduces, thus increasing the power density of the converter. This paper finds how significant is the effect of shifting gate pulse on output voltage ripples in CI-SIDO boost converter. The analysis is valid for different values of duty ratios and coupled inductor parameters. The analysis is verified by simulation in MATLAB Simulink.