16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR ADCs with a large interleaving factor suffer from a large input capacitance [1] and often have a limited BW, or otherwise they necessitate a power-hungry broadband input buffer [2]. Flash ADCs [3] not only face the same challenge from the large input parasitics but also limited resolutions resulting from offset. Recently, time-domain ADCs [4], [5] have shown promising speeds resulting from a small input capacitance due to their inherent voltage-to-time converter (VTC) as a sub-channel wideband buffer, but also show limited resolution (6b) due to the mismatches between the time steps. When targeting a higher resolution [6], calibration is necessary to unify the time quantization steps and often requires a known input condition with a large lookup table, thus introducing complexity. In this work, a 10 GS/s ADC is achieved by just aggregating four 8b two-stage time-domain ADCs running at 2.5GS/s. The gain between the stages is inherently defined by a 16x time interpolator in the second stage, which not only saves power but also allows the time quantization steps to be free from calibration. The presented time-domain ADC achieves >37.5dB SNDR at an 18GHz input due to its small input capacitance and buffer-like VTC, and also obtains a metastability error rate <; 10
^-8
through a timing-extended residue transfer scheme. Moreover, the time quantization in the two-stage ADC also shows PVT robustness benefits from the interpolation-based gain.