3-Phase Adiabatic Logic and its Sound SCA Evaluation

Nowadays there is no doubt on the susceptibility of pure cryptographic devices to side-channel analysis attacks. During the last decade, integration of corresponding countermeasures into devices which deal with security and privacy of the users has become a must. This motivated several research on designing countermeasures, one of which is to make use of power-balancing feature of adiabatic logic families which have been originally motivated for low-power applications. In this work we introduce the first such a construction which operates in three phases compared to the entire state-of-the-art schemes requiring at least four phases. We especially designed our proposed scheme to harden power-analysis SCA attacks. To this end, we considered several relevant design criteria. For example, we payed particular attention to the symmetry of the fundamental gates of our proposed 3-phase construction. Based on simulation results and information-theoretic based SCA evaluations we claim that our construction can harden power analysis attacks more than the state-of-the-art adiabatic logic families. We further highlight the importance of the way power clocks are generated for an adiabatic circuit, and show the negative effect of the widely-known stepwise charge sharing power clock generator on the SCA security. Accordingly, we present an adjustment on such a circuit followed by corresponding SCA evaluation of its application on various adiabatic logic families.