Static Low-Power 17T True Single Phase Clocking Flip-Flop Based on Logic Structure Optimization

Flip flops (FFs) are the fundamental storage components abundantly used in digital system designs, which involves pipelining structures and modules built by FFs. The FFs contribute a major amount to total power consumption and significant amount to chip area of the digital system. So, there is a need for low power and low area FF designs. In this paper, a fully static very-low power 17- transistor True Single Phase Clocking (TSPC) flip-flop is proposed. The logic structure of Proposed TSPC FF is of master- slave type in which master stage is formed by static CMOS logic and slave is formed by a mixed combination of static CMOS logic and complementary pass transistor logic. The Proposed TSPC FF circuit is fully static because no internal nodes are in floating state during the operation which actually prevents leakage power dissipation. The proposed TSPC FF is designed by optimizing 19-transistor Logic Structure Reduction Flip Flop (LRFF) with respect to area and power consumption, but without compromising the functionality of the FF. The design of three FFs namely Transmission Gate Based Flip Flop (TGFF), LRFF and Proposed TSPC FF are implemented and simulated using gpdk45nm technology library with supply voltage V
_DD
of 1V and clock frequency of 500MH
_z
in cadence virtuoso tool. Pre-layout simulation results indicates that the proposed TSPC FF shows an improvement in power delay product (PDP) up to 67.32% and 21.58% compared to that of TGFF and LRFF respectively at 10
^%
data switching activity. The number of transistors required to design proposed TSPC FF is reduced by seven and two compared to that of TGFF and LRFF respectively.