Low-Complexity High Speed Memory Based Real Fast Fourier Transform (RFFT) Architecture with Carry Increment and Pipelined Adders

In today's the rapid development of technology, area, delay and power are the most important factors to design any kind of algorithm on Field Programmable Gate Arrays (FPGA). The aim of this work is to design an efficient 32-point Radix-2 memory based Real Fast Fourier Transform (RFFT) computation for the real-valued signals. The proposed RFFT architecture can deliver a maximum throughput rate and lesser hardware complexity by using a Processing Element (PE), which is utilized in the RFFT architecture. Compared with the previous works the proposed RFFT architecture with Carry Increment Adder (CIA) and pipelined adder technique has a main advantage of less hardware usage and moreover reduction in the computation cycles. The experimental results shows that Look-up tables (LUT), slices, flip flops, frequency improved in RFFT architecture with CIA and pipelined adder compared with the existing methods.