A Low Power mixed Signal Foreground Calibration Technique of a Pipeline ADC using a Variable Gain Amplifier

This paper proposes a foreground calibration technique of a pipeline ADC, using a mixed signal back-end calibration circuit. This calibration circuit contains only a digital comparator and a 1
^st
order low pass filter (LPF). At the front end analog part, a variable gain amplifier (VGA) responds to the back-end unit to calibrate a pipeline stage gain. Unlike typical radix extraction principle of a background or foreground calibration technique, the proposed technique forces the gain of the multiplying-DAC (MDAC) of a 1.5-bit target stage to 2 V/V. To achieve this, the sampling capacitor ( CS) and the feedback capacitor ( CF) of the said stage are ratio-ed with a skew of > 2. In order to compensate the skew, a gain controllable VGA is tuned to such a gain so that overall gain of the MDAC becomes exactly equal to 2 V/V or the ideal gain. In this paper, an 11-bit pipeline ADC has been simulated which contains a 1.5-bit non-ideal pipeline stage followed by a 10-bit back-end ADC (BE-ADC). Simulations have been performed to compare the linearity of the ADC at different gain value of the VGA. With an initial VGA gain value of 15 V/V and 35 V/V, the calibration algorithm iterates to final value of VGA gain of A=24.55 V/V, when the calibration loop breaks. Behavioural simulation of this 11-bit pipeline ADC shows that at Nyquist rate, after calibration, SNDR, SFDR and ENOB are 64.73 dB, 74.02 dB and 10.46 bits respectively.