Impact of the S/D extension doping profile on the /spl Psi/-cell concept

The viability of the /spl Psi/-cell concept that has been proposed for CMOS embedded flash applications is examined as the CMOS dimensions shrink down. More specifically, we focus on the dependence of the memory operation on the doping profile underneath the spacer. We show that for optimum operation of the /spl Psi/-cell concept below 0.18 μm CMOS technologies, the S/D extension implantation process step should be omitted.