Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis

Threshold logic circuits are artificial neural networks with their neuron outputs being binarized, thus amenable for efficient, multiplierfree, hardware implementation of machine learning applications. In the reviving threshold logic synthesis, this work lays the foundations of disjoint-support decomposition and extraction operation of threshold logic functions. They lead to a synthesis procedure for interconnect minimization of threshold logic circuits, an important, but not well addressed, objective in both neural network and nanometer circuit designs. Experimental results show that our method can efficiently and effectively reduce interconnect as well as weight/threshold value over highly optimized circuits, thus suitable for implementation using emerging technologies.