Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method

High efficiency video coding (HEVC) uses large size of discrete cosine transforms (DCT), which increases hardware complexity quadratically. However, higher order DCTs are used less than 10% of the time and can tolerate some approximation without any noticeable degradation in the coding performance. Therefore, to reduce the computational complexity, an approximation algorithm is proposed in this paper. To achieve this, a new generalized model for the HEVC compliance DCT kernel is proposed using the Walsh Hadamard transform (WHT)-based matrix decomposition method. Thereafter, the proposed approximation algorithm replaces the rotation unit by a butterfly structure with minimum normality error. Four approximated architectures are implemented to provide different tradeoffs between coding accuracy and hardware complexity. Those architectures are less complex compared to the other architectures, and the coding performance is also better. The CMOS 90-nm ASIC implementation of the proposed 1-D DCT architecture requires 111.23k logic gates at 250-MHz operating frequency without any approximation. However, with the approximation algorithm, 43%-82% savings in the area-delay product are possible. When implemented on the Virtex-7 FPGA, the proposed approximated architecture reduces power consumption by 70% compared to that of the HEVC reference architecture to maintain a reasonable tradeoff between accuracy and complexity.