Incremental Sturdy-MASH Sigma-Delta Modulator with Reduced Sensitivity to DAC Mismatch

Incremental Sigma-Delta (ΣΔ) modulators inherit internal oversampling and noise-shaping properties of a conventional ΣΔ modulator. However, by resetting its internal states, as well as the digital reconstruction filter after certain number of clock cycles, a sample-by-sample conversion behavior is obtained and the modulator can be considered as a Nyquist-rate converter. Multibit architectures allow for low oversampling ratios and can be very attractive for high speed applications. Yet, it comes with digital-to-analog converter (DAC) linearity concerns and commonly used linearization techniques such as dynamic element matching are inefficient when acquired in an Incremental ΣΔ modulator, due to the resetting environment and especially for very low OSRs. This paper presents an enhanced incremental sturdy multi-stage noise-shaping ΣΔ modulator structure, which utilizes a variable quantizer bit width in the second stage for linearity improvement. The behavioral simulations of the proposed architecture show its robustness against DAC mismatch, achieving 25 dB improvement in total harmonic distortion in the presence of 0.1% DAC element mismatch with an OSR of 35.