Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication process for superconductor electronics that integrates two layers of Josephson junctions (JJs) in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional superconductor-insulator-superconductor (SIS) Nb/Al/AlOx/Nb junctions with the same or different Josephson critical current densities, Jc. The process also allows integration of high-Jc superconductor-ferromagnet-superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlOx/Nb trilayer junctions on the second JJ layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target critical current densities for the SIS JJs are 100 μA/μm
²
and 200 μA/μm
²
. We present the salient features of the new process, fabrication details, and characterization results on two layers of JJs integrated into one process, both for the conventional and π-junctions.