Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g
_max
=198 mS/mm and an I/sub dast/ of 0.3 mA/μm at V/sub g/-V
_T
=1.5 V, with L/sub G/=0.4 μm and t/sub ox/=110 /spl Aring/. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS.