Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage

Intellectual property protection techniques face a challenging task in countering a physical attack by reverse engineering the netlist of an embedded integrated circuit. An attacker can extract sensitive information with image tools by processing microphotographs at low metal layers of delayered chips. We propose a low performance and zero-area impact method to obfuscate circuits by using a current digital design flow with a layout standard cell generator to obtain different physical versions of the same logic cell. Results indicate that timing and power overhead, introduced by the obfuscation method, can be mitigated. After applying the method to a set of benchmark circuits and a 32-bit RISC-based microprocessor, results show a 40%-50% average obfuscation with zero area penalty and less than 2% timing and power penalty for system level blocks. Considering that most attacks direct reverse engineering to key cryptographic functions, experimental obfuscation results indicate a timing penalty of 4% with a strong obfuscation level for a synthesized key establishment core.