A Novel Design of a 47GHz Programmable Frequency Divider based on RLTSPC logic in 65nm CMOS

This paper presents a CMOS high speed frequency divider which can operate at up to 47GHz based on a chain of 2/3 prescaler. A novel 2/3 prescaler structure using logic gate embedded RLTSPC D flip-flop is proposed minimized the critical delay to reach 47GHz. The following stage 2/3 prescaler is also optimized compared to conventional structure, to reduce circuit complexity and power consumption. The proposed frequency divider is implemented in 65nm CMOS process, and exhibits phase noise of -158.3 dBc/Hz@10MHz offset and power consumption of 1.3mW.