A High-Speed Pipelined ADC Based on Open-Loop Amplification

In this paper, a high-speed pipelined ADC is proposed based on open-loop amplification. The open loop amplification technology presents higher bandwidth and higher power efficiency than the conventional closed loop amplification. Source degeneration technology is adopted to improve the linearity of the residual amplifier. In addition, each stage outputs one bit for higher conversion rate and more flexibility. The sample and hold amplifier is remove for power efficiency. The ADC is implemented in 0.18 CMOS process. The simulation result shows than an SNDR of 55.09 dB and an SFDR of 67.37 dB are achieved at a sampling rate of 500 Msps and the power consumption is about 181 mW.