A 1-V 90.3-dB DR 100-kHz BW 4th-Order Single Bit Sigma-Delta Modulator in 40-nm CMOS Technology

A 1-V 4th-order discrete-time single bit sigma-delta modulator over a signal bandwidth of 100 kHz is presented in this paper. The feed forward topology is selected to reduce the voltage swings of the integrators. In addition, a novel two-stage inverter-based amplifier is proposed to improve the DC gain in low voltage environment. To save power consumption, a pure dynamic comparator is employed. Designed and implemented in 40-nm CMOS technology, the modulator achieves 88.5 dB peak SNDR (signal-to-noise and distortion ratio) and 90.3 dB DR (dynamic range). The core area of the chip is 0.133 mm
²
and the total power consumption is 1 mW.