Hardware Implementation of Parallel FIR Filter Using Modified Distributed Arithmetic

We proposed a area efficient architecture implementation of finite impulse response (FIR) Filter using Distributed Arithmetic. Area complexity in the fir filter is mainly increased for the multipliers. To overcome this drawback the multiplier less techniques distributed arithmetic is most preferred area efficient technique to implement FIR filter. In this technique, partial products of filter coefficients and input sample are precomputed and stored in lookup table (LUT) and multiplication is done by shift and accumulate operations on these partial products. However, the size of the LUT will increase exponentially with the increase of number of coefficient that means no of order of the filter. If the co-efficient is small, it is very convenient to implement. While the coefficient is large, it will take up a lot of storage resources of FPGA and reduce the calculation speed. This report presents the modification of the Distributed Arithmetic algorithm by partitioning the LUT size and parallelism in the FIR filter by processing multiple bit at a time. We presented 16-tap FIR filter in serial and parallel mode, with different size of memory partitioning of LUT and synthesis result shows improvement in performance in terms of speed as well as saving in area. The proposed architecture using vhdl model are synthesized with Xilinx ISE 14.4.