Built-in self-test and fault diagnosis for lookup table FPGAs

A novel built-in self-test structure for the lookup table (LUT) based field programmable gate arrays (FPGA's) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLB's) is assumed. The whole chip is partitioned into disjoint one-dimensional arrays of cells. We assume that in each linear array, there is at most one faulty cell, and a faulty cell may contain multiple faulty CLB's. Our idea is to configure the cells to make each cell function bijective. In order to detect all faults defined, k+2 configurations are required. The input patterns can be easily generated with a k-bit counter and the fault coverage is 100%. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB.