A pipelined multiply-accumulate unit design for energy recovery DSP systems

A pipelined 15/spl times/15 bit multiply-accumulate (MAC) unit, optimized for energy recovery systems, is presented. The applied architectural and circuit level optimizations are aimed at minimizing the total non-recoverable energy per computation. For that purpose, the number of pipeline stages is minimized, utilizing logic gates based on high fan-in differential NMOS trees. The MAC includes three pipeline stages operated from a two-phase non-overlapping power clock and processes one multiply-accumulate operation per clock cycle. Implemented in 0.25 /spl mu/m CMOS process and powered from a 1 V power supply, this circuit uses 4.5 pJ of recoverable energy per clock cycle, while dissipating 0.28 pJ of non-recoverable energy.