Speeding up hardware prototyping by incremental simulation/emulation

We describe a method for the automatic construction of a testbench, able to dynamically communicate a standard VHDL simulator with a logic emulator by means of text files. The proposed approach significantly reduces turn-around times in an emulation based rapid system prototyping environment. In this way, time-consuming logic synthesis and technology mapping steps are moved, in the design cycle, after a previous functional verification.