Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication

Digital implementations of the Fast Fourier Transform (FFT) are widely used in communication systems using Orthogonal frequency-division multiplexing. These systems currently comprise several communication standards such as IEEE 802.11agjn, IEEE 802.20 mobile wireless broadband access, asymmetric digital subscriber lines and digital audio and video broadcasting. Thus, this work proposes a methodology using a multiple constant multiplication (MCM) solution to optimize single stage, radix-2 decimation-in-time FFT processors. It uses the algorithm proposed by Cooley and Tukey to determine the coefficients of the FFT and the algorithm proposed by Aksoy et al. to solve the MCM problem. Also, we develop an algorithm that automatically elaborates FFT architectures using SystemVerilog hardware description language. Each design is functionally verified and logically synthesized utilizing the XFAB 0.18μm cells library. The usage of this methodology reduces the number of real multiplications implemented in 58.33 - 30.96% on architectures from 8 up to 256 input points. Also, mean squared error is kept below 2.5% and SNR higher than 52dB.