A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation

This paper presents a hardware design for the 3D-High Efficiency Video Coding (3D-HEVC) Disparity Estimation (DE) based on the Unidirectional Disparity Search (UDS) algorithm. The architecture was developed to process the four square-shaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes. These two design approaches caused a coding efficiency degradation of only 0.554% in the BD-rate when compared to the traditional approach whereas allowed a significant reduction in the required calculations and also in the memory accesses, contributing to generate a fast and energy-efficient design. The architecture has a high level of parallelism to reach the desired high throughput and explored clock gating to reduce the power dissipation. As the best of the author's knowledge, this is the first work on literature presenting a hardware design for the 3D-HEVC DE. The architecture was ASIC synthesized and can reach up to 1.457 GHz. This result allows a processing rate of five views of UHD 2160p videos at 52 frames per second. When compared with related works targeting the HEVC Motion Estimation, the developed architecture uses a smaller area, requires a smaller memory, reaches a higher throughput and dissipates at least 92% less power.