High Throughput Multiplierless Architecture for VP9 Fractional Motion Estimation

This paper presents a dedicated hardware design for the Fractional Motion Estimation (FME) of VP9 encoders. The presented hardware was designed to reach real-time when processing high definition videos. The designed FME filters use pure combinational logic. The multiplications were designed through shift-adds and the common sub-expressions were shared to reduce the hardware area and to increase the architecture throughput. Two architectural versions were designed, targeting two video resolutions. These architectural versions have distinct levels of parallelism and reach different throughputs. The synthesis was targeted to 45nm Nangate standard-cells technology, and the results show that the architecture with the highest parallelism has the performance to process Full HD videos (1920×1080 pixels) at 30 frames per second with a power dissipation of 569.9mW. To the best of our knowledge, there is no other published work with dedicated hardware for a complete VP9 FME design.