Work-in-Progress: Hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

To minimize size, weight, power and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.