A systolic array RLS processor

This paper describes the outline of the systolic array recursive least-squares (RLS) processor that we developed primarily with the aim of broadband mobile communication applications. To perform the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board is comprised of 19 application-specific integrated circuit chips, each having approximately one million gates. 32-bit fixed point signal processing takes place in the processor, with which one cycle of internal cell signal processing requires about 500 nsec, and boundary cell signal processing about 80 nsec. The processor board can estimate up to 10 parameters and takes approximate 35 /spl mu/s to estimate 10 parameters by using 41 known symbols. To evaluate this processor, we conduct minimum mean-squared error adaptive array in-lab experiments using a complex baseband fading/array response simulator. In terms of parameter estimation accuracy, the processor is found to produce virtually the same results as a conventional software engine using floating-point operations.