GPSAT: A SAT based Global Placement for Large Scale Mixed-size Designs

In this paper, a novel Boolean SAT based wirelength-driven global placement technique has been presented. Among the three conventional steps (global placement, legalization and detailed placement) for complete placement of VLSI circuits, we have done up to global placement. Global placement is the basis of other two phases in placement. Hence, importance of global placement is very high in the row of placement problem.To achieve good placement solutions, a new hierarchical cluster- ing technique has been introduced to divide the set of circuit components into clusters in order to reduce the complexity of the global placement problem based on fixed circuit blocks and their connections with other movable blocks. An area partitioning method is proposed to divide the placement area into hierarchical regions which helps to find wirelength-driven global placement for the circuit components considering pin offsets and pin directions using SAT. Different components of a given circuit are placed cluster-wise using Boolean satisfiability. All the algorithms have been tested and implemented on ISPD 2011 benchmark circuits. The proposed technique exhibits 6% improvement in terms of wirelength compare to other existing placers.