A Low-Power Digital Pixel Driving Scheme for Single-Pulse-PWM-Based Display Using AND-Embedded Pixel Circuits

A new digital pixel driving scheme is presented for reducing power in the column-line drivers in a single-pulse-PWM-based display. Rather than updating the digital pixel memory value for every access of the memory, the proposed driving scheme utilizes the property that there are only two level transitions in a single-pulse PWM for representing a digital value. With the use of AND-embedded SRAM pixel memory and simple logic controlling the AND gates, this minimizes the number of column-line signal transitions as the row-line scanning progresses. As a result, power dissipation in the column-line drivers is greatly reduced compared to the case of using a conventional digital pixel driving scheme. A quantitative analysis describing the number of column-line signal transitions for both the conventional and proposed schemes agrees well with the simulation results for random digital inputs and real sample images as well, verifying the efficacy on power reduction in the column-line drivers. Including power dissipation by the circuits controlling the AND gates in the pixel memories, power reduction efficiency for many different image samples is at least more than 50%.