A Highly Digital Second-Order Oversampling TDC

A second-order, single loop ΔΣ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.