Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and 25 Ω and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.