Ultra-Dense Ring-Shaped Racetrack Memory Cache Design

Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the bi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational performances. In this paper, we propose a non-volatile cache design based on spin-orbit torque-driven ring-shaped RM. The systematical investigations, covering from device modeling, to circuits design, to bit-cell layout design, and to system evaluation have been carried out. Thanks to the cells-overlapping design, the proposed RM L2 cache can achieve 48×, 16×, and 8× improvements in term of capacity, compared with iso-area caches based on static random access memory (SRAM), spin transfer torque magnetic RAM (STT-MRAM), and tape-shaped RM, respectively. As proved by 4-core system experiment results, the proposed RM cache can improve 30.7% instructions per cycle (IPC) and save 58.2% energy compared with SRAM cache.