An algorithmic approach to building datapath multipliers using (3,2) counters

Traditionally multipliers have been laid out manually, using simple delay models for the counters. However, at deep submicron feature sizes, these delay models do not accurately model the resulting delays. Therefore, an algorithmic approach to the design of the multiplier is required. This paper presents an algorithm that connects the counters of the multiplier, under the constraint of a limited number of available wiring tracks. The algorithm uses an advanced delay model for the (3-2) counter. This delay model includes the incremental delay due to the placement and wiring of the counters. The algorithm has been implemented and the resulting program has been used to compare several designs of an IEEE floating point multiplier using several delay models.