Integration of Metallization Processes in Robust Interconnects Formation for 14 nm Nodes and beyond

In this communication the results of metallization processes integration to create robust Cu interconnects for advanced 14 nm and beyond nodes are presented. Conventional Dual Damascene Back End of the Line (BEOL) process flow to form 64 nm pitch on-chip Cu interconnects in low-k dielectric substrate was utilized. TaN barrier, Ta liner layers followed by Cu seed were formed by physical vapor deposition (PVD). Cu lines were fabricated by electrochemical plating (ECP) of Cu followed by Chemical Mechanical Polishing (CMP).