An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3-D ICs

Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time-consuming for the drop test simulation, and therefore the fast numerical approach is needed to reduce the computational cost. In this paper, we propose an efficient drop test simulator for through-silicon-via (TSV)based 3-D IC to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second-order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. Second, an equivalent structure-embedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop test simulator can achieve 7.03× speedup in comparison with the conventional finite-element method-based solver. It is demonstrated in this paper through several examples with multichip layers, of which each chip layer consists of an 8 × 8 TSV array, that the proposed simulator can be widely applied to reliability analysis of 3-D ICs under drop impact.