Wafer Level Embedding Technology for Packaging of Planar GaN Half-Bridge Module in High Power Density Conversion Applications

For the development of GaN-based power solutions, electronic packaging aspects like high temperature capability, low parasitics and low thermal resistance have to be considered for final robust systems. A new fabrication process is here presented for packaging of GaN bare devices in form of silicon-based packages using wafer level back-end processes. Compact planar half-bridge modules were fabricated at 200 mm wafer scale with 650 V rated single GaN bare die. The package demonstrates voltage breakdown up to 650 V with leakage current as low as 250 nA with top-bottom electrical isolation of 1 nA at 2500V. A thermal resistance RthJC of around 0.4 K/W was also characterized. Implementation in power solutions has been first evaluated and first results will be presented in this paper.