White Rabbit Clock Synchronization: Ultimate Limits on Close-In Phase Noise and Short-Term Stability Due to FPGA Implementation

This paper investigates the ultimate limits of White Rabbit (WR), an high-accuracy time distribution system based on field-programmable gate array (FPGA). The knowledge of such limits is essential for new emerging applications that are evaluating WR. In this paper, we identify and study the key elements in the WR synchronization: the digital dual mixer time difference phase detector and the Gigabit Ethernet transceiver. The benchmarks and experimental analysis of these key elements allow us to determine the WR switch (WRS) performance limits and evaluate their evolution with newer FPGAs. The identified performance limits are achievable by the present-day generation of WRS. The ultimate limits of short-term synchronization performance due to FPGA implementation have been derived through analysis and then demonstrated using the existing WRS enhanced with an additional daughterboard. This combination (WRS and daughterboard) achieves a tenfold improvement in terms of phase noise, jitter, and short-term stability with respect to the current WR performance. Both phase detectors and Gigabit transceivers have a similar phase noise contribution equal to a short-term stability of modified Allan deviation 4E-13 at τ = 1 s (dominated by flicker phase modulation noise).