A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption

The asynchronous paradigm is an alternative that can solve the synchronous design problems caused by the global clock signal that are being worse in the Deep-Sub-Micron CMOS Technology (DSM-CMOS). Asynchronous controllers are important components in a digital design. A controller class quite familiar to designers is the burst-mode asynchronous finite state machines (BM-AFSMs). BM-AFSMs interact with the environment in the fundamental mode (FM), therefore they need a timing analysis and the response of the environment must be slow enough for the BM-AFSMs to accept the response, that is, to be stable. For environments that respond quickly BM-AFSMs may violate FM. Violation of the FM requires the insertion of delay elements into the status variables, which degrades performance, reliability and area. In this, paper we propose a design flow for the class of Non-FM-BM-AFSMs, i.e., novel machines interacting with the environment without the assumption of FM and are robust to delay variations in the gates, so they are free of timing analysis. The proposed design flow was applied to eleven BM benchmarks. In addition to obtaining the relaxation of the FM mode, it also obtained respectively an average reduction of 17% and 0% in the number of products and 26% and 11% in the number of literals when compared to the Minimalist and 3D tools that are the main synthesis tools of BM-AFSMs operating in the FM.