ASIC power-estimation accuracy evaluation: A case study using video-coding architectures

This paper presents an evaluation of different power-estimation flows in standard-cell ASIC synthesis using video-coding architectures as a case study. For estimating the power, the Encounter RTL Compiler and iRun tools are used with the 45nm Nangate standard-cell library. Four power-estimation flows were evaluated: A) based on default switching activity provided by the tool, B) based on previous statistical switching analysis, and two considering real input data - C) based on the RTL files and D) based on the netlist files - being the last one the Cadence recommended flow for these tools. These power-estimation flows are compared according to simulation time, designer's expertise, net assert (when applied), and mainly about the power estimation accuracy. The case study used to compare these flows consists of two dedicated video-coding hardware, being a purely combinational and a pipelined architectures. The results show that the flow widely used in the literature papers, using only the RTL files and the default switching active provided by the tool, can present more than 40% of relative error for the evaluated designs, when compared with the Cadence recommended flow.