Memristor models optimization for large-scale 1T1R memory arrays

Recently, memristive devices have been shown to possess unique and intriguing properties such as small size, high density, non-volatility, state-dependent behavior, good scalability, very low leakage current, and compatibility with CMOS technology. When using memristive devices at the circuit level a major requirement is the availability of a simple, accurate and efficient model that adequately characterizes circuit performance. Most existing models for memristive devices presented in the literature suffer from high complexity and computational inefficiency. In this paper, we propose a new scheme to reduce the computational complexity of existing models and improve simulation time while maintaining circuit designer requirements in terms of accuracy. Using this technique, the simulation time can be improved by around 20% while maintaining a good accuracy.