A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (ADC) implemented in a conventional 1.2-/spl mu/m CMOS process is presented. Low voltage, large signal swing sample-and-hold, and digital-to-analog conversion are realized based on inverting op-amp configurations with biasing currents added to the op-amp negative input terminal so that the op-amp input common-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at half of the supply rails. A low-voltage latched comparator is realized based on the current-mode approach. The entire ADC including all the digital circuits consumes less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal.