Synthesis analysis and evaluation of hardware scheduler based on different scheduling algorithms

The limitations of the current real-time operating systems are given by the CPU architecture, the memory, and the I/O subsystem, but also by the high-level languages and their compilers, and the unpredictable answer of the asynchronous interrupts. The most important issue of a real time system is resource scheduling: processor, memory, I/O ports and communication networks, when systems are distributed. The present article gives an overview of the state of the art of qualitative research in terms of tasks schedulability algorithms used for the nMPRA (Multi Pipeline Register Architecture) CPU architecture in real-time environments. By introducing a jitter of maximum three clock cycles for the contexts switching of tasks, the nMPRA processor proves a deterministic hardware implementation, due to the integrated nHSE (Hardware Scheduler Engine for n tasks). This paper presents and analyzes the current state of real time operation systems with hardware implementation functions.