Modified RS encoder architecture with reduced critical path delay for high speed data communication

In this digital era the cause of the current trend for wireless applications is the improved data rate for multifarious applications of communication. But during communication, the data might be distorted due to impairments of channels. Decrease in errors because of distorted channels becomes significant. RS encoder with reduced critical path delay for data storage communication is presented in this paper. With minimum delay data can be transmitted at high rate on using pipelining and parallelizing techniques. By transforming the LFSR into the form of an Infinite Impulse Response (IIR) filter the increased delay in the basic LFSR based Reed Solomon encoder is eradicated. The projected architecture results in high speed and reduced critical path with less hardware overhead. A case representing the parallel and pipelined design of an encoder is given for (15, 11) RS code. The proposed design produces a delay of 2.39nS at the rate of 418.59MHz.