An approach to LUT based multiplier for short word length DSP systems

Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look-up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents a way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP elements for Short Word Length DSP system (multiplier) is also carried out as an alternative implementation approach. Result suggests the proposed way be the better one when compared with other two implementations.