On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration

A gain and offset-calibrated 3-state phase detector is proposed to accurately measure static phase difference. Forcing the phase detector to operate in two different modes provides the full-scale gain since the sum of the two results is 2π. Flipping the inputs and averaging the results cancels the offset. Proposed circuit enhancements realize a robust reset and a gain, independent of waveform rise/fall times. A 0.13-μm CMOS prototype of the proposed enhanced phase detector has errors ≤ 0.5° for 2.4-GHz quadrature inputs. It consumes 3.6 mA from 1.2V and occupies 0.0416 mm
²
. The proposed circuit can be used for on-chip measurement and calibration of multi-phase clock generators in radios and clocking circuits.