A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method

Todays world is digital and therefore digital communication plays a vital role in communication systems. Viterbi algorithm invented by Andrew J. Viterbi is widely used for error correction of communication devices. Due to the high performance, Viterbi Decoder is broadly used to decode the convolutional codes. One third area is occupied by Viterbi decoders while chip manufacturing. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed three methods for survivor path storage and decoding as Register Exchange Method (REM), Hybrid Register Exchange Method (HREM) and Minimum Transition Hybrid Register Exchange Method (MTHREM). But as we designed and simulate the Viterbi decoder using above mentioned methods we observed that the REM consumes more power and area as it gives high switching activity. We combines the two techniques as Traceback and REM called HREM for further reduction in switching activity at every cycle. Both the methods has their own drawbacks. To reduce power by controlling α switching activity and also the unwanted transitions from one register to other at every time interval we introduced the new techniques called MTHREM. Viterbi decoders designed using REM, HREM and MTHREM is simulated and power is calculated using Power play power analyzer. As the switching activity is reduced in MTHREM as compared to REM and HREM the Viterbi decoder achieves reduction in power in MHREM as compared to REM and HREM. For further reduction in power of Viterbi decoder we proposed asynchronous techniques like Handshaking protocol. Here we designed the Asynchronous Viterbi decoder by using Level encoded dual rail encoding (LEDR).