An 800-MHz Mixed- $V_{\text{T}}$ 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional static random access memory (SRAM) due to its high-density, low-leakage, and inherent two-ported operation, yet its dynamic nature leads to limited retention time and calls for periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances lead to accelerated data integrity deterioration. The emerging approximate computing paradigm utilizes the inherent error-resilience of different applications to tolerate some errors in the stored data. Such error tolerance can be exploited to reduce the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption at the cost of an increase in cell failure probability. In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28-nm bulk CMOS technology. The array, which is based on a novel mixed-VT four-transistor (4T) gain cell with internal feedback (IFGC) optimized for high performance, features a small silicon footprint and supports high-performance operation. The proposed memory can be used with conservative (i.e., 100% reliable) computing paradigms, but also in the context of approximate computing, featuring a small silicon footprint and random access bandwidth. Silicon measurements demonstrate successful operation at 800 MHz under a 900-mv supply while retaining between 30% and 45% lower bitcell area than a single-ported six-transistor (6T) SRAM and a two-ported six-transistor (8T) SRAM in the same technology.