An 8.52–11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor

The proposed time-voltage-time convertor (TVTC) based quadrature clock generator (QCG) utilizes digitally controlled delay line (DCDL) and phase mixer to generate four-phase clock and a feedback path to detect the difference in amplitudes of the four-phase clocks. By adjusting the DCDL adaptively, the QCG gives quadrature clock with ultra-low phase error. TVTC can improve the effective resolution of the DCDL by 3.66 times without degrading the tuning range of the DCDL, which ranges from 8.52 GHz to 11.34 GHz. With the help of TVTC, the phase error of the quadrature clock is reduced by 82% compared with DLL's. The proposed QCG reduces the use of supply-sensitive DCDL, which reduces the supply noise by 75.1%. The QCG is designed in 65 nm CMOS process. The phase error of the proposed QCG is 0.34° @ 10 GHz. The QCG consumes 12.7 mW from a 1.2 V supply voltage.