An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme

In this paper, an ultra-low-power true single-phase clocking flip-flop (FF) design is proposed. The design follows a master-slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and pass-transistor logic (PTL). In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving low power and short delay performance. Comparing with the conventional transmission gate flip-flop (TGFF), the proposed flip-flop reduced power-delay product (PDP) by 62.3% under 12.5% data switching activity. Moreover, the circuit also achieves better hold time variation and is implemented with TSMC 90-nm CMOS technology.