Area-performance-power analysis of hand gesture recognition system in FPGA

In this paper, we have designed a hand gesture recognition system that can detect static hand gestures and analyze its performance and resource utilization on different FPGA architectures and verify its operation through software hardware co-simulation. Various parameters like resource utilization, area performance, power consumption of the proposed design has been determined after successful testing of the design on two different FPGA architectures, viz. Virtex-5 and Spartan-6. A thorough analysis of the results indicates that both the target devices work equally well in regards to area utilization, Spartan-6 performs slower as compared to Virtex-5, while Virtex-5 consumes more power for the same design in comparison to Spartan-6.