Exploring different execution paradigms in exposed datapath architectures with buffered processing units

Exposed datapath processor architectures allow the software to bypass register usage by directly moving intermediate results between processing units with suitable instructions. Synchronous Control Asynchronous Dataflow (SCAD) is a new exposed datapath architecture consisting of a grid of processing units with buffers to store their input and output values. Code generation inspired from queue machines can utilize the bypassing capability of such exposed datapath architectures with buffered processing units and can completely eliminate the use of registers this way. In this paper, we consider different execution paradigms of SCAD that make a compromise between hardware complexity, hardware scalability, and the use of instruction-level parallelism. To that end, we study both resource- and time-optimal code for all variants that we determine by satisfiability modulo theories (SMT) solvers. Experimental results show that the execution paradigm followed by our original SCAD architecture makes a reasonable compromise between hardware complexity and the use of instruction-level parallelism while maintaining hardware scalability.