Test power optimization using clock gating

The major factor in VLSI design process is low power testing. Modern ICs consists of more transistors in a single chip due to which testing becomes challenging since it consumes more power than functionality of the circuits. System clock signal in electronics product consumes the important part of dynamic power, among them 70% is spent by clock buffers. This problem can be solved using a technique known as Clock Gating. Here a traditional Linear Feedback Shift Register (LFSR) without clock gating technique is first implemented and the output is then compared with LFSR designed using different Clock Gating techniques. This proposed TPG using Clock Gating reduces the switching activity among the test patterns at the most.